This invention relates to a duplex data processing system, and particularly to a bus connecting facility for linking two processors.
Information processing systems, such as electronic exchanges, which operate uninterruptedly are often provided with a duplex arrangement for processors each consisting of a central processing unit (CPU), memory unit, I/O controller and CPU bus for connecting these units in order to prevent system shutdown caused by a failure. Methods of information communication between the two processors include provision of a common memory unit for both processors, and automatic data transfer for a specific storage area in the memory unit of one processor to that of another processor. However, conventional duplex methods invariably designate the two processors to be operate as an active system and a stand-by system, respectively, and therefore they necessitate very complicated system control. Data processing systems of this type are described in Japanese Patent Publication No. 58-54421 and Japanese Patent Unexamined Publication No. 59-125422.